/*
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/

/**********************************************************************************************************************
 * File Name    : spi_iobitmask.h
 * Version      : 1.00
 * Description  : IO bit mask file for spi.
 *********************************************************************************************************************/

#ifndef SPI_IOBITMASK_H
#define SPI_IOBITMASK_H

#define R_SPI_B0_SPDECR_SCKDL_Pos     (0UL)          /*!< SCKDL (Bit 0)                                         */
#define R_SPI_B0_SPDECR_SCKDL_Msk     (0x7UL)        /*!< SCKDL (Bitfield-Mask: 0x07)                           */
#define R_SPI_B0_SPDECR_SLNDL_Pos     (8UL)          /*!< SLNDL (Bit 8)                                         */
#define R_SPI_B0_SPDECR_SLNDL_Msk     (0x700UL)      /*!< SLNDL (Bitfield-Mask: 0x07)                           */
#define R_SPI_B0_SPDECR_SPNDL_Pos     (16UL)         /*!< SPNDL (Bit 16)                                        */
#define R_SPI_B0_SPDECR_SPNDL_Msk     (0x70000UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
#define R_SPI_B0_SPDECR_ARST_Pos      (24UL)         /*!< ARST (Bit 24)                                         */
#define R_SPI_B0_SPDECR_ARST_Msk      (0x7000000UL)  /*!< ARST (Bitfield-Mask: 0x07)                            */
#define R_SPI_B0_SPCR_SPE_Pos         (0UL)          /*!< SPE (Bit 0)                                           */
#define R_SPI_B0_SPCR_SPE_Msk         (0x1UL)        /*!< SPE (Bitfield-Mask: 0x01)                             */
#define R_SPI_B0_SPCR_SPSCKSEL_Pos    (7UL)          /*!< SPSCKSEL (Bit 7)                                      */
#define R_SPI_B0_SPCR_SPSCKSEL_Msk    (0x80UL)       /*!< SPSCKSEL (Bitfield-Mask: 0x01)                        */
#define R_SPI_B0_SPCR_SPPE_Pos        (8UL)          /*!< SPPE (Bit 8)                                          */
#define R_SPI_B0_SPCR_SPPE_Msk        (0x100UL)      /*!< SPPE (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCR_SPOE_Pos        (9UL)          /*!< SPOE (Bit 9)                                          */
#define R_SPI_B0_SPCR_SPOE_Msk        (0x200UL)      /*!< SPOE (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCR_PTE_Pos         (11UL)         /*!< PTE (Bit 11)                                          */
#define R_SPI_B0_SPCR_PTE_Msk         (0x800UL)      /*!< PTE (Bitfield-Mask: 0x01)                             */
#define R_SPI_B0_SPCR_SCKASE_Pos      (12UL)         /*!< SCKASE (Bit 12)                                       */
#define R_SPI_B0_SPCR_SCKASE_Msk      (0x1000UL)     /*!< SCKASE (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCR_BFDS_Pos        (13UL)         /*!< BFDS (Bit 13)                                         */
#define R_SPI_B0_SPCR_BFDS_Msk        (0x2000UL)     /*!< BFDS (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCR_MODFEN_Pos      (14UL)         /*!< MODFEN (Bit 14)                                       */
#define R_SPI_B0_SPCR_MODFEN_Msk      (0x4000UL)     /*!< MODFEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCR_SPEIE_Pos       (16UL)         /*!< SPEIE (Bit 16)                                        */
#define R_SPI_B0_SPCR_SPEIE_Msk       (0x10000UL)    /*!< SPEIE (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCR_SPRIE_Pos       (17UL)         /*!< SPRIE (Bit 17)                                        */
#define R_SPI_B0_SPCR_SPRIE_Msk       (0x20000UL)    /*!< SPRIE (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCR_SPIIE_Pos       (18UL)         /*!< SPIIE (Bit 18)                                        */
#define R_SPI_B0_SPCR_SPIIE_Msk       (0x40000UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCR_SPDRES_Pos      (19UL)         /*!< SPDRES (Bit 19)                                       */
#define R_SPI_B0_SPCR_SPDRES_Msk      (0x80000UL)    /*!< SPDRES (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCR_SPTIE_Pos       (20UL)         /*!< SPTIE (Bit 20)                                        */
#define R_SPI_B0_SPCR_SPTIE_Msk       (0x100000UL)   /*!< SPTIE (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCR_CENDIE_Pos      (21UL)         /*!< CENDIE (Bit 21)                                       */
#define R_SPI_B0_SPCR_CENDIE_Msk      (0x200000UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCR_SPMS_Pos        (24UL)         /*!< SPMS (Bit 24)                                         */
#define R_SPI_B0_SPCR_SPMS_Msk        (0x1000000UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCR_SPFRF_Pos       (25UL)         /*!< SPFRF (Bit 25)                                        */
#define R_SPI_B0_SPCR_SPFRF_Msk       (0x2000000UL)  /*!< SPFRF (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCR_TXMD_Pos        (28UL)         /*!< TXMD (Bit 28)                                         */
#define R_SPI_B0_SPCR_TXMD_Msk        (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03)                            */
#define R_SPI_B0_SPCR_MSTR_Pos        (30UL)         /*!< MSTR (Bit 30)                                         */
#define R_SPI_B0_SPCR_MSTR_Msk        (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCR_BPEN_Pos        (31UL)         /*!< BPEN (Bit 31)                                         */
#define R_SPI_B0_SPCR_BPEN_Msk        (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCR2_RMFM_Pos       (0UL)          /*!< RMFM (Bit 0)                                          */
#define R_SPI_B0_SPCR2_RMFM_Msk       (0x1fUL)       /*!< RMFM (Bitfield-Mask: 0x1f)                            */
#define R_SPI_B0_SPCR2_RMEDTG_Pos     (6UL)          /*!< RMEDTG (Bit 6)                                        */
#define R_SPI_B0_SPCR2_RMEDTG_Msk     (0x40UL)       /*!< RMEDTG (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCR2_RMSTTG_Pos     (7UL)          /*!< RMSTTG (Bit 7)                                        */
#define R_SPI_B0_SPCR2_RMSTTG_Msk     (0x80UL)       /*!< RMSTTG (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCR2_SPDRC_Pos      (8UL)          /*!< SPDRC (Bit 8)                                         */
#define R_SPI_B0_SPCR2_SPDRC_Msk      (0xff00UL)     /*!< SPDRC (Bitfield-Mask: 0xff)                           */
#define R_SPI_B0_SPCR2_SPLP_Pos       (16UL)         /*!< SPLP (Bit 16)                                         */
#define R_SPI_B0_SPCR2_SPLP_Msk       (0x10000UL)    /*!< SPLP (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCR2_SPLP2_Pos      (17UL)         /*!< SPLP2 (Bit 17)                                        */
#define R_SPI_B0_SPCR2_SPLP2_Msk      (0x20000UL)    /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCR2_SPOM_Pos       (18UL)
#define R_SPI_B0_SPCR2_SPOM_Msk       (0x40000UL)
#define R_SPI_B0_SPCR2_MOIFV_Pos      (20UL)         /*!< MOIFV (Bit 20)                                        */
#define R_SPI_B0_SPCR2_MOIFV_Msk      (0x100000UL)   /*!< MOIFV (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCR2_MOIFE_Pos      (21UL)         /*!< MOIFE (Bit 21)                                        */
#define R_SPI_B0_SPCR2_MOIFE_Msk      (0x200000UL)   /*!< MOIFE (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCR2_SPSCKDL_Pos    (24UL)
#define R_SPI_B0_SPCR2_SPSCKDL_Msk    (0x7000000UL)
#define R_SPI_B0_SPCR3_SSL0P_Pos      (0UL)          /*!< SSL0P (Bit 0)                                         */
#define R_SPI_B0_SPCR3_SSL0P_Msk      (0x1UL)        /*!< SSL0P (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCR3_SSL1P_Pos      (1UL)          /*!< SSL1P (Bit 1)                                         */
#define R_SPI_B0_SPCR3_SSL1P_Msk      (0x2UL)        /*!< SSL1P (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCR3_SSL2P_Pos      (2UL)          /*!< SSL2P (Bit 2)                                         */
#define R_SPI_B0_SPCR3_SSL2P_Msk      (0x4UL)        /*!< SSL2P (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCR3_SSL3P_Pos      (3UL)          /*!< SSL3P (Bit 3)                                         */
#define R_SPI_B0_SPCR3_SSL3P_Msk      (0x8UL)        /*!< SSL3P (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCR3_SPBR_Pos       (8UL)          /*!< SPBR (Bit 8)                                          */
#define R_SPI_B0_SPCR3_SPBR_Msk       (0xff00UL)     /*!< SPBR (Bitfield-Mask: 0xff)                            */
#define R_SPI_B0_SPCR3_SPSLN_Pos      (24UL)         /*!< SPSLN (Bit 24)                                        */
#define R_SPI_B0_SPCR3_SPSLN_Msk      (0x7000000UL)  /*!< SPSLN (Bitfield-Mask: 0x07)                           */
#define R_SPI_B0_SPCMD0_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
#define R_SPI_B0_SPCMD0_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD0_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
#define R_SPI_B0_SPCMD0_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD0_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
#define R_SPI_B0_SPCMD0_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
#define R_SPI_B0_SPCMD0_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
#define R_SPI_B0_SPCMD0_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCMD0_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
#define R_SPI_B0_SPCMD0_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD0_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
#define R_SPI_B0_SPCMD0_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD0_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
#define R_SPI_B0_SPCMD0_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD0_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
#define R_SPI_B0_SPCMD0_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD0_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
#define R_SPI_B0_SPCMD0_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
#define R_SPI_B0_SPCMD0_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
#define R_SPI_B0_SPCMD0_SSLA_Msk      (0x3000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
#define R_SPI_B0_SPCMD1_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
#define R_SPI_B0_SPCMD1_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD1_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
#define R_SPI_B0_SPCMD1_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD1_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
#define R_SPI_B0_SPCMD1_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
#define R_SPI_B0_SPCMD1_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
#define R_SPI_B0_SPCMD1_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCMD1_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
#define R_SPI_B0_SPCMD1_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD1_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
#define R_SPI_B0_SPCMD1_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD1_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
#define R_SPI_B0_SPCMD1_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD1_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
#define R_SPI_B0_SPCMD1_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD1_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
#define R_SPI_B0_SPCMD1_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
#define R_SPI_B0_SPCMD1_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
#define R_SPI_B0_SPCMD1_SSLA_Msk      (0x3000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
#define R_SPI_B0_SPCMD2_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
#define R_SPI_B0_SPCMD2_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD2_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
#define R_SPI_B0_SPCMD2_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD2_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
#define R_SPI_B0_SPCMD2_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
#define R_SPI_B0_SPCMD2_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
#define R_SPI_B0_SPCMD2_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCMD2_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
#define R_SPI_B0_SPCMD2_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD2_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
#define R_SPI_B0_SPCMD2_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD2_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
#define R_SPI_B0_SPCMD2_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD2_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
#define R_SPI_B0_SPCMD2_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD2_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
#define R_SPI_B0_SPCMD2_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
#define R_SPI_B0_SPCMD2_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
#define R_SPI_B0_SPCMD2_SSLA_Msk      (0x3000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
#define R_SPI_B0_SPCMD3_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
#define R_SPI_B0_SPCMD3_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD3_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
#define R_SPI_B0_SPCMD3_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD3_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
#define R_SPI_B0_SPCMD3_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
#define R_SPI_B0_SPCMD3_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
#define R_SPI_B0_SPCMD3_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCMD3_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
#define R_SPI_B0_SPCMD3_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD3_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
#define R_SPI_B0_SPCMD3_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD3_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
#define R_SPI_B0_SPCMD3_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD3_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
#define R_SPI_B0_SPCMD3_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD3_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
#define R_SPI_B0_SPCMD3_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
#define R_SPI_B0_SPCMD3_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
#define R_SPI_B0_SPCMD3_SSLA_Msk      (0x3000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
#define R_SPI_B0_SPCMD4_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
#define R_SPI_B0_SPCMD4_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD4_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
#define R_SPI_B0_SPCMD4_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD4_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
#define R_SPI_B0_SPCMD4_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
#define R_SPI_B0_SPCMD4_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
#define R_SPI_B0_SPCMD4_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCMD4_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
#define R_SPI_B0_SPCMD4_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD4_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
#define R_SPI_B0_SPCMD4_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD4_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
#define R_SPI_B0_SPCMD4_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD4_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
#define R_SPI_B0_SPCMD4_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD4_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
#define R_SPI_B0_SPCMD4_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
#define R_SPI_B0_SPCMD4_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
#define R_SPI_B0_SPCMD4_SSLA_Msk      (0x3000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
#define R_SPI_B0_SPCMD5_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
#define R_SPI_B0_SPCMD5_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD5_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
#define R_SPI_B0_SPCMD5_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD5_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
#define R_SPI_B0_SPCMD5_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
#define R_SPI_B0_SPCMD5_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
#define R_SPI_B0_SPCMD5_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCMD5_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
#define R_SPI_B0_SPCMD5_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD5_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
#define R_SPI_B0_SPCMD5_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD5_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
#define R_SPI_B0_SPCMD5_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD5_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
#define R_SPI_B0_SPCMD5_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD5_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
#define R_SPI_B0_SPCMD5_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
#define R_SPI_B0_SPCMD5_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
#define R_SPI_B0_SPCMD5_SSLA_Msk      (0x3000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
#define R_SPI_B0_SPCMD6_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
#define R_SPI_B0_SPCMD6_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD6_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
#define R_SPI_B0_SPCMD6_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD6_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
#define R_SPI_B0_SPCMD6_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
#define R_SPI_B0_SPCMD6_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
#define R_SPI_B0_SPCMD6_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCMD6_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
#define R_SPI_B0_SPCMD6_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD6_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
#define R_SPI_B0_SPCMD6_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD6_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
#define R_SPI_B0_SPCMD6_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD6_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
#define R_SPI_B0_SPCMD6_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD6_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
#define R_SPI_B0_SPCMD6_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
#define R_SPI_B0_SPCMD6_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
#define R_SPI_B0_SPCMD6_SSLA_Msk      (0x3000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
#define R_SPI_B0_SPCMD7_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
#define R_SPI_B0_SPCMD7_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD7_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
#define R_SPI_B0_SPCMD7_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD7_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
#define R_SPI_B0_SPCMD7_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
#define R_SPI_B0_SPCMD7_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
#define R_SPI_B0_SPCMD7_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPCMD7_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
#define R_SPI_B0_SPCMD7_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPCMD7_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
#define R_SPI_B0_SPCMD7_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD7_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
#define R_SPI_B0_SPCMD7_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD7_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
#define R_SPI_B0_SPCMD7_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPCMD7_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
#define R_SPI_B0_SPCMD7_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
#define R_SPI_B0_SPCMD7_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
#define R_SPI_B0_SPCMD7_SSLA_Msk      (0x3000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
#define R_SPI_B0_SPDCR_BYSW_Pos       (0UL)          /*!< BYSW (Bit 0)                                          */
#define R_SPI_B0_SPDCR_BYSW_Msk       (0x1UL)        /*!< BYSW (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPDCR_SLSEL_Pos      (1UL)
#define R_SPI_B0_SPDCR_SLSEL_Msk      (0x6UL)
#define R_SPI_B0_SPDCR_SPRDTD_Pos     (3UL)          /*!< SPRDTD (Bit 3)                                        */
#define R_SPI_B0_SPDCR_SPRDTD_Msk     (0x8UL)        /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPDCR_SINV_Pos       (4UL)          /*!< SINV (Bit 4)                                          */
#define R_SPI_B0_SPDCR_SINV_Msk       (0x10UL)       /*!< SINV (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPDCR_SPFC_Pos       (8UL)          /*!< SPFC (Bit 8)                                          */
#define R_SPI_B0_SPDCR_SPFC_Msk       (0xF00UL)      /*!< SPFC (Bitfield-Mask: 0x03)                            */
#define R_SPI_B0_SPDCR2_RTRG_Pos      (0UL)          /*!< RTRG (Bit 0)                                          */
#define R_SPI_B0_SPDCR2_RTRG_Msk      (0xFUL)        /*!< RTRG (Bitfield-Mask: 0x03)                            */
#define R_SPI_B0_SPDCR2_TTRG_Pos      (8UL)          /*!< TTRG (Bit 8)                                          */
#define R_SPI_B0_SPDCR2_TTRG_Msk      (0xF00UL)      /*!< TTRG (Bitfield-Mask: 0x03)                            */
#define R_SPI_B0_SPSR_SPCP_Pos        (8UL)          /*!< SPCP (Bit 8)                                          */
#define R_SPI_B0_SPSR_SPCP_Msk        (0x700UL)      /*!< SPCP (Bitfield-Mask: 0x07)                            */
#define R_SPI_B0_SPSR_SPECM_Pos       (12UL)         /*!< SPECM (Bit 12)                                        */
#define R_SPI_B0_SPSR_SPECM_Msk       (0x7000UL)     /*!< SPECM (Bitfield-Mask: 0x07)                           */
#define R_SPI_B0_SPSR_SPDRF_Pos       (23UL)         /*!< SPDRF (Bit 23)                                        */
#define R_SPI_B0_SPSR_SPDRF_Msk       (0x800000UL)   /*!< SPDRF (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPSR_OVRF_Pos        (24UL)         /*!< OVRF (Bit 24)                                         */
#define R_SPI_B0_SPSR_OVRF_Msk        (0x1000000UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPSR_IDLNF_Pos       (25UL)         /*!< IDLNF (Bit 25)                                        */
#define R_SPI_B0_SPSR_IDLNF_Msk       (0x2000000UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPSR_MODF_Pos        (26UL)         /*!< MODF (Bit 26)                                         */
#define R_SPI_B0_SPSR_MODF_Msk        (0x4000000UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPSR_PERF_Pos        (27UL)         /*!< PERF (Bit 27)                                         */
#define R_SPI_B0_SPSR_PERF_Msk        (0x8000000UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPSR_UDRF_Pos        (28UL)         /*!< UDRF (Bit 28)                                         */
#define R_SPI_B0_SPSR_UDRF_Msk        (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPSR_SPTEF_Pos       (29UL)         /*!< SPTEF (Bit 29)                                        */
#define R_SPI_B0_SPSR_SPTEF_Msk       (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPSR_CENDF_Pos       (30UL)         /*!< CENDF (Bit 30)                                        */
#define R_SPI_B0_SPSR_CENDF_Msk       (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPSR_SPRF_Pos        (31UL)         /*!< SPRF (Bit 31)                                         */
#define R_SPI_B0_SPSR_SPRF_Msk        (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
#define R_SPI_B0_SPTFSR_TFDN_Pos      (0UL)          /*!< TFDN (Bit 0)                                          */
#define R_SPI_B0_SPTFSR_TFDN_Msk      (0x1FUL)       /*!< TFDN (Bitfield-Mask: 0x07)                            */
#define R_SPI_B0_SPRFSR_RFDN_Pos      (0UL)          /*!< RFDN (Bit 0)                                          */
#define R_SPI_B0_SPRFSR_RFDN_Msk      (0x7UL)        /*!< RFDN (Bitfield-Mask: 0x07)                            */
#define R_SPI_B0_SPPSR_SPEPS_Pos      (0UL)          /*!< SPEPS (Bit 0)                                         */
#define R_SPI_B0_SPPSR_SPEPS_Msk      (0x1UL)        /*!< SPEPS (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPSRC_SPDRFC_Pos     (23UL)         /*!< SPDRFC (Bit 23)                                       */
#define R_SPI_B0_SPSRC_SPDRFC_Msk     (0x800000UL)   /*!< SPDRFC (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPSRC_OVRFC_Pos      (24UL)         /*!< OVRFC (Bit 24)                                        */
#define R_SPI_B0_SPSRC_OVRFC_Msk      (0x1000000UL)  /*!< OVRFC (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPSRC_MODFC_Pos      (26UL)         /*!< MODFC (Bit 26)                                        */
#define R_SPI_B0_SPSRC_MODFC_Msk      (0x4000000UL)  /*!< MODFC (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPSRC_PERFC_Pos      (27UL)         /*!< PERFC (Bit 27)                                        */
#define R_SPI_B0_SPSRC_PERFC_Msk      (0x8000000UL)  /*!< PERFC (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPSRC_UDRFC_Pos      (28UL)         /*!< UDRFC (Bit 28)                                        */
#define R_SPI_B0_SPSRC_UDRFC_Msk      (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPSRC_SPTEFC_Pos     (29UL)         /*!< SPTEFC (Bit 29)                                       */
#define R_SPI_B0_SPSRC_SPTEFC_Msk     (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPSRC_CENDFC_Pos     (30UL)         /*!< CENDFC (Bit 30)                                       */
#define R_SPI_B0_SPSRC_CENDFC_Msk     (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01)                          */
#define R_SPI_B0_SPSRC_SPRFC_Pos      (31UL)         /*!< SPRFC (Bit 31)                                        */
#define R_SPI_B0_SPSRC_SPRFC_Msk      (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01)                           */
#define R_SPI_B0_SPFCR_SPFRST_Pos     (0UL)          /*!< SPFRST (Bit 0)                                        */
#define R_SPI_B0_SPFCR_SPFRST_Msk     (0x1UL)        /*!< SPFRST (Bitfield-Mask: 0x01)                          */

#endif
